1. Field of the Invention
The present invention relates to semiconductor devices, particularly to a semiconductor device including a plurality of internal circuits using a plurality of power supply potentials respectively.
2. Description of the Background Art
In a semiconductor device receiving a plurality of external power supply potentials, a great amount of through current may flow depending upon the sequence of turning on the power supply. For example, a level conversion circuit is known as such a circuit through which through current flows. When the first external power supply potential is higher than the second external power supply potential in a semiconductor device receiving the first and second external power supply potentials, through current will flow through the level conversion circuit that converts the level of the second external power supply potential to the level of the first external power supply potential in the semiconductor device.
In the event that the second external power supply potential is first applied, and then the first external power supply potential is applied, no through current will flow. However, if the external power supply potentials are applied in an opposite order, there will be a flow of through current.
The through current in a level conversion circuit will be described with reference to the drawings.
FIG. 21 is a diagram to describe the symbols employed in the present specification.
Referring to FIG. 21, a P channel MOS transistor 502, an N channel MOS transistor 504 and an inverter 506 are circuit elements formed of MOS transistors whose gate oxide films are of the thin type employed in the circuit where a power supply potential Ext.Vcc2 corresponding to the second external power supply potential is used as the operating power supply potential.
In contrast, a P channel MOS transistor 508, an N channel MOS transistor 510 and an inverter 512 are circuit elements formed of MOS transistors whose gate oxide films are thick in the circuit where a power supply potential Ext.Vcc1 corresponding to the first external power supply potential higher than the second internal power supply potential is used as the operating power supply potential. A higher voltage can be applied by setting the gate oxide film thicker.
FIG. 22 is a circuit diagram showing a structure of a first conventional level conversion circuit converting the H level of a signal to a higher potential from a lower potential.
Referring to FIGS. 21 and 22, the level conversion circuit includes an inverter 518 receiving and inverting a signal SIG, an N channel MOS transistor 520 having a gate receiving signal SIG and a source connected to the ground node, an N channel MOS transistor 522 receiving the output of inverter 518 and having a source connected to the ground node, a P channel MOS transistor 514 connected between the node receiving external power supply potential Ext.Vcc1 and the drain of N channel MOS transistor 520, having its gate connected to the drain of N channel MOS transistor 522, and a P channel MOS transistor 516 connected between the node receiving power supply potential Ext.Vcc1 and the drain of N channel MOS transistor 522, and having a gate connected to the drain of N channel MOS transistor 520.
From the drain of N channel MOS transistor 522 is output a signal /SIG with the amplitude between 0 V and power supply potential Ext.Vcc1. Signal /SIG is an inverted and level-converted version of signal SIG with the amplitude between 0 V and external power supply potential Ext.Vcc2.
Inverter 518 receives external power supply potential Ext.Vcc2 as the operating power supply potential. Therefore, inverter 518 is formed of a thin film transistor, i.e. a transistor with a thin gate oxide film. The other transistors 514, 516, 520 and 522 are the so-called thick film transistors with thick gate oxide films.
Through current flows through this level conversion circuit when external power supply potential Ext.Vcc1 is applied and power supply potential Ext.Vcc2 is not yet applied. More specifically, when signal SIG is in the vicinity of the threshold voltage of N channel MOS transistor 520 or at a higher intermediate potential, a through current Ic1 flows to N channel MOS transistor 520. When power supply potential Ext.Vcc1 is applied and power supply potential Ext.Vcc2 is not yet applied, the output of inverter 518 exhibits an unstable state. If the gate potential of N channel MOS transistor 522 is in the vicinity of the threshold voltage or at a higher intermediate potential, a through current Ic2 flows to N channel MOS transistor 522.
FIG. 23 is a circuit diagram showing a structure of a second conventional level conversion circuit converting the H level signal from a high potential to a low potential.
Referring to FIGS. 21 and 23, the level conversion circuit includes a P channel MOS transistor 582 receiving a signal SIGA at its gate and having its source connected to external power supply potential Ext.Vcc2, and an N channel MOS transistor 584 receiving signal SIGA at its gate, and connected between the drain of P channel MOS transistor 582 and the ground node. A signal /SIGA is output from the drain of P channel MOS transistor 582.
Signal SIGA has an L level corresponding to 0 V and an H level corresponding to power supply potential Ext.Vcc1. Signal /SIGA has an L level corresponding to 0 V and an H level corresponding to power supply potential Ext.Vcc2. It is to be noted that power supply potential Ext.Vcc2 is lower than power supply potential Ext.Vcc1. Transistors 582 and 584 are transistors with a gate oxide film of a thickness that can withstand power supply voltage Ext.Vcc1. Even in such a circuit of the above-described structure, through current will flow when the potential of external power supply potential Ext.Vcc1 is not yet applied at the state where the potential of external power supply potential Ext.Vcc2 is sufficiently high if signal SIGA is at the intermediate potential, i.e. in the vicinity exceeding the threshold voltage of N channel MOS transistor 584.
The through current at the time of power-on is basically great in any electrical product. Under the requirement of reducing such a through current as much as possible, it is not desirable that a semiconductor device has a structure that increases the through current at the time of power-on as shown in FIG. 22. If the order of power-on is defined, the usability of the semiconductor device will be deteriorated from the user""s side.
The level conversion circuit shown in FIG. 22 is used mainly in the following two cases.
The first case is where both of external power supply potentials Ext.Vcc1 and Ext.Vcc2 are used as the operating power supply potentials of the internal circuit, wherein external power supply potential Ext.Vcc1 is higher than power supply potential Ext.Vcc2. In the event of applying a signal from the circuit with Ext.Vcc2 as the operating power supply potential to a circuit with Ext.Vcc1 as the operating power supply potential, the path of the through current in the level conversion circuit must be disconnected. A structure for this purpose must be implemented.
The second case of the level conversion circuit is when a signal is to be delivered from a circuit with Ext.Vcc2 as the operating power supply potential to a circuit with a higher internal power supply potential as the operating power supply potential, wherein this internal power supply potential is generated internally from external power supply potential Ext.Vcc1.
In this case, a level conversion circuit is employed having an internal power supply potential applied instead of power supply potential Ext.Vcc1 in the level conversion circuit of FIG. 22. A structure that disconnects the through current path of the level conversion circuit or a structure that suppresses the generation of the internal power supply potential in the case power supply potential Ext.Vcc2 is not yet high enough must be implemented.
An object of the present invention is to provide a semiconductor device capable of reducing through current when including an internal circuit using a plurality of power supply potentials.
According to an aspect of the present invention, a semiconductor device includes a first terminal, a second terminal, a sense circuit, and an internal circuit.
The first terminal receives a first power supply potential. The second terminal receives a second power supply potential. The sense circuit receives an operating power supply potential from the first terminal to sense the potential of the second terminal. The internal circuit receives an input signal applied according to the potential of the second terminal to operate according to the output of the sense circuit.
A main advantage of the present invention is that a semiconductor device receiving a plurality of power supply potentials can detect that the power supply potential has not risen and cause the internal circuit to carry out a predetermined operation to reduce through current.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.